With increasing numbers of transistors being formed on devices such as Ultra Large Scale Integration (ULSI) chips, additional demands are being placed upon the wiring and Input-Output (I.O.) processes. For example, the levels of interconnection metals required to wire the complex micro processors continues to increase. Because of the increased complexity, lower yield and cost associated with the metallurgy it would, in some cases be desirable to construct smaller chips, placing more of the wiring levels in the packaging. In order to accomplish this, without impacting performance, a large number of I.O. connections are required. One current I.O. structure design that is extensively used is the bumped chip or Controlled Collapse Chip Connect (C4) technology. As presently conceived it can provide up to a few thousand I.O.'s on a large chip, however, there is a need in the industry for higher I.O. densities.
The C4 pads size are currently limited by the ability to produce small holes in metal shadow masks that are employed to determine both pad and solder diameters. The masks must be or sufficient thickness to prevent warpage or damage during use or cleaning. This then limits the minimum hole size which can be economically produced. One current C4 process uses a layer of solder that is deposited after the formation of the pads and subsequently reflowed to form solder balls.
One approach to the need for higher density I.O. structures includes a solder transfer technique that selectively places individual solder bumps on a chip or wafer. Individual placement of solder allows for a smaller quantity of solder to be deposited, and allows a tighter position tolerance than shadow mask techniques. One individual placement method includes the use of a piezoelectric solder ball print-head. However, Curie temperatures of useful ceramics for piezoelectrics impose a practical limitation on the maximal operating temperatures of such print-heads. Because currently known ceramics for piezoelectrics cannot effectively operate at temperatures greater than about 300° C., solder material selection is limited and optimal jetting characteristics, such as solder viscosity and surface tension are compromised in piezoelectric print-head designs. Furthermore, piezoelectric printing devices are expensive to manufacture. Designs that incorporate large numbers of channels to apply large arrays of solder balls at high speed are cost prohibitive using piezoelectric designs.
What is needed is an individual placement method and apparatus that is capable of meeting increasingly demanding feature size and tolerance concerns. What is also needed is an individual placement method and apparatus that is capable of operating at high temperatures. What is also needed is an individual placement method and apparatus that is inexpensive to manufacture and operate.